The present invention relates to computer memory, and more particularly, to a system and method for allowing memory devices having defective memory locations to be used in high accuracy applications.
Substantially all modern electronic computers rely on semiconductor memory to store data for processing by a central processing unit (CPU). Such computers employing semiconductor memory vary from simple computers, such as those contained in telephone answering machines, to highly complex supercomputers employed for complicated scientific projects. In simple computers like those used for telephone answering machines, errors in one or more of the memory locations of the memory may not be fatal. For example, a mistake in the memory of the telephone answering machine likely would only cause the synthesized voice stored on the memory to be imperceptibly altered. However, one or more defective memory locations in a memory of a computer used to perform scientific calculations may cause substantial problems.
Although current manufacturing techniques have substantially reduced the number of defective memory locations, excessive numbers of defective memory locations are still sometimes produced during fabrication of computer memory. Those defective memory locations can be caused by any of numerous steps taken during manufacture of the memory chips, semiconductor crystallinity defects, electrical connector discontinuities, etc. Although memory chips with such defective memory locations typically represent a small portion (less than 1%) of the total number of memory chips produced, the actual number of such defective memory chips is substantial. In some cases, such defective memory chips could be sold at a greatly reduced price for applications that do not require perfect memory, such as for telephone answering machines. However, it would be beneficial if some of those memory chips could be employed in more critical applications, such as in personal computers.
Several prior art error handling schemes have been employed to compensate for defective memory locations. For example, one error handling scheme employs extra rows of memory cells, known as xe2x80x9credundant rows,xe2x80x9d that could be used to replace rows having defective memory cells. While the use of redundant rows is often successful in salvaging otherwise defective memory chips, the number of defective rows that can be replaced is limited to the number of redundant rows that are provided on the memory chip. The number of defective rows sometimes exceeds the number of redundant rows, thus preventing repair of some defective rows.
Another prior art error handling scheme, known as error detection, detects when a single bit of a data word is in error. Error detection typically adds a single parity bit to each data word written to memory in order to make the sum of the data word and the parity be an even number. If the sum of the data word and the parity bit is an odd number when the data word is read, then the error detection scheme determines that one of the bits of the data word is in error. Such parity-based error detection often is inadequate because only single bit errors are detected, the particular bit in error is not identified, and the particular bit in error is not corrected.
Yet another error handling scheme, known as error correction, overcomes some of the deficiencies in prior art error detection schemes. Hardware error correction schemes add to each data word plural error correction bits that enable the data word to be reconstituted in the event of an erroneous data bit within the data word. However, such prior art error correction schemes typically only reconstitute a data word if only a single bit of the data word is erroneous. Moreover, such error correction schemes add several extra data bits to each data word which results in high memory overhead. In addition, such error correction schemes could be extended to correct multiple erroneous data bits, but the memory overhead that would result likely would be unacceptable.
Although each of the prior art error handling schemes provide some protection for defective memory locations, none of them are perfect. Some require excessive memory overhead while others provide inadequate protection. Moreover, prior art error handling schemes are employed on a system-wide basis, that is, the entire working memory of a computer system is accessed according to a single error handling system regardless of the applications for which the computer system is being used.
A preferred embodiment of the present invention is directed to a method and computer system for storing data subject to memory errors. The preferred embodiment includes a memory controller with a plurality of different error handing modules, each of which can be selectively associated with one or more memory blocks. Each of the error handling modules is structured to write data to and read data from its associated memory block according to a different error handling scheme. Preferably, the error handling modules include an error detection module, an error correction module, and a memory remapping module. In addition, preferably there is also an option for the memory controller to write data to and read data from a memory block without performing any error handling.
In the preferred embodiment, the memory controller includes a separate configuration register for each of the plurality of memory blocks. Each configuration register stores an indication of the error handling module that will be employed to write data to and read data from the memory block associated with the configuration register. Such configuration registers enable the computer system designer or users to specify which error handling module is most appropriate for the associated error block based on the applications for which the memory blocks will be employed.